tools that read the VHDL, and output The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis a definition of the physical implementation of the circuit.
II. Objectives
- to be able to implement logic circuit design in VHDL codes.
III. Conceptual Framework
IV. Data and Results
2.1 Create VHDL code for 4 bits to 7-segment decoder
library IEEE;
use IEEE.std_logic_1164.all;
entity MNM21 is
port ( I: in std_logic_vector (3 downto 0);
O: out std_logic_vector (6 downto 0));
end MNM21;
architecture twopoint1 of MNM21 is
begin
process (I)
begin
case I is
when "0000" => O <= "0000001";
when "0001" => O <= "1001111";
when "0010" => O <= "0010010";
when "0011" => O <= "0000110";
when "0100" => O <= "1001100";
when "0101" => O <= "0100100";
when "0110" => O <= "0100000";
when "0111" => O <= "0001111";
when "1000" => O <= "0000000";
when "1001" => O <= "0000100";
when "1010" => O <= "0001000";
when "1011" => O <= "1100000";
when "1100" => O <= "0110001";
when "1101" => O <= "1000010";
when "1110" => O <= "0110000";
when "1111" => O <= "0111000";
end case;
end process;
end twopoint1;
2.2 Create VHDL code for generic multiplexer 8 to 1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity MNM22 is
port ( SEL: in std_logic_vector (0 to 2);
A,B,C,D,E,F,G,H: in std_logic;
MUX: out std_logic);
end MNM22;
architecture twopoint2 of MNM22 is
begin
process (SEL)
begin
case SEL is
when "000" => MUX <= A;
when "001" => MUX <= B;
when "010" => MUX <= C;
when "011" => MUX <= D;
when "100" => MUX <= E;
when "101" => MUX <= F;
when "110" => MUX <= G;
when "111" => MUX <= H;
end case;
end process;
end twopoint2;
V. Analysis
VI.Conclusion
